The internal processor clock cycle is determined by the current core-clock to busclock ratio.

For Pentium M processors (family, models ) for Pentium 4 processors, Intel Xeon processors (family, models ) and for P6 family processors: the time-stamp counter increments with every internal processor clock cycle.

Intel processor families increment the time-stamp counter differently: The programmer can solve this problem by inserting a serializing instruction, such as CPUID, to force every preceding instruction to complete before allowing the program to continue, or by using the RDTSCP instruction, which is a serializing variant of the RDTSC instruction. This can cause the processor to execute RDTSC later than a simple program expects, producing a misleading cycle count. Starting with the Pentium Pro, Intel processors have practiced out-of-order execution, where instructions are not necessarily performed in the order they appear in the program. On POSIX systems, a program can get similar function by reading the value of CLOCK_MONOTONIC clock using the clock_gettime function. On Windows platforms, Microsoft strongly discourages using the TSC for high-resolution timing for exactly these reasons, providing instead the Windows APIs QueryPerformanceCounter and QueryPerformanceFrequency.

Hence TSC ticks are counting the passage of time, not the number of CPU clock cycles elapsed. With these processors, the TSC ticks at the processor's nominal frequency, regardless of the actual CPU clock frequency due to turbo or power saving states. Recent Intel processors include a constant rate TSC (identified by the _tsc sysctl on FreeBSD or by the ' constant_tsc' flag in Linux's /proc/cpuinfo). Relying on the TSC also reduces portability, as other processors may not have a similar feature. In those latter cases, to stay relevant, the program must re-calibrate the counter periodically.

Even then, the CPU speed may change because of power-saving measures taken by the OS or BIOS, or the system may be hibernated and later resumed, resetting the TSC. Therefore, a program can get reliable results only by limiting itself to run on one specific CPU. There is no promise that the timestamp counters of multiple CPUs on a single motherboard will be synchronized.

With the advent of multi-core/hyper-threaded CPUs, systems with multiple CPUs, and hibernating operating systems, the TSC cannot be relied upon to provide accurate results - unless great care is taken to correct the possible flaws: rate of tick and whether all cores (processors) have identical values in their time-keeping registers. The Time Stamp Counter was once an excellent high-resolution, low-overhead way for a program to get CPU timing information.

Free time stamp program